射孔枪+内置式压力计托筒+水力泵新三联作试油(测试)工艺技术在大港油田研制与应用

该工艺技术是在原三联作(TCP+MFE+JET)基础上,根据大港油田勘探试油(测试)的需要,研制开发出的又一新技术,与原三联作相比,一趟管柱不但完成求产、测压、泵排工作,而且还能进行酸化等措施,提高了资料品质,减少了作业成本。经过6井次现场应用,全部达到了设计要求,取得了工艺、资料、成本、速度的较大进步,具有较高推广应用价值。     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

HIST: A hierarchical self test methodology for chips,boards, and systems

This article presents the HIST approach, which allows the automated insertion of self test hardware into hierarchically designed circuits and systems to implement the RUNBIST instruction of the IEEE 1149.1 standard. To achieve an optimal and throughout self testable system, the inherent design hierarchy is fully exploited. All chips and boards are provided with appropriate test controllers at each hierarchy level. The approach is able to detect all those faults, which are in the scope of the underlying self test algorithms. In this paper the hierarchical test architecture, the test controllers as well as all necessary synthesis procedures are presented. Finally a successful application of the HIST approach to a cryptography processor is described.     

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test

A system-on-chip (SOC) usually consists of many memory cores with different sizes and functionality, and they typically represent a significant portion of the SOC and therefore dominate its yield. Diagnostics for yield enhancement of the memory cores thus is a very important issue. In this paper we present two data compression techniques that can be used to speed up the transmission of diagnostic data from the embedded RAM built-in self-test (BIST) circuit that has diagnostic support to the external tester. The proposed syndrome-accumulation approach compresses the faulty-cell address and March syndrome to about 28% of the original size on average under the March-17N diagnostic test algorithm. The key component of the compressor is a novel syndrome-accumulation circuit, which can be realized by a content-addressable memory. Experimental results show that the area overhead is about 0.9% for a 1Mb SRAM with 164 faults. A tree-based compression technique for word-oriented memories is also presented. By using a simplified Huffman coding scheme and partitioning each 256-bit Hamming syndrome into fixed-size symbols, the average compression ratio (size of original data to that of compressed data) is about 10, assuming 16-bit symbols. Also, the additional hardware to implement the tree-based compressor is very small. The proposed compression techniques effectively reduce the memory diagnosis time as well as the tester storage requirement.     

基于模板的．Net三层架构的代码自动生成

三层架构是数据库开发中最常用的分层架构。三层结构能够提高代码重用率,降低项目开发难度。为了解决手工编写三层架构的代码工作量大且容易出错的问题,使用．Net平台提供的动态编译和反射技术,设计并实现了基于可定制模板的自动代码生成器。该代码生成器利用三层架构的代码依赖数据库的架构信息这一特点,以数据库架构信息、Xml配置文件和模板文件作为输入,输出三层架构的各层代码。用户可以修改Xml配置文件的内容和使用该代码生成器提供的模板语言定制、修改自己的模板文件,方便、灵活地控制输出的目标代码。代码生成器的使用在实际的项目开发中具有重要的意义。     

关于JSP线程安全问题的思考

JSP中变量的定义有全局和局部之分,局部变量并不会带来安全问题,而对全局变量的使用,就要慎之又慎。内置对象application的使用要特别注意线程安全。此外,JavaBean的使用也要注意线程安全问题,特别是当scope属性设置为application的时候。     

Exact probabilistic testability measures for multi-output circuits

The computation of probabilistic testability measures has become increasingly important and some methods have been proposed, although the exact solution of the problem is NP-hard. An exact analytical method for singleoutput combinational circuits is extended to deal with multi-output circuits. Such circuits are reduced to singleoutput ones by introducing a dummy gate, the X-gate, and applying to the resulting graph the analysis based on supergates.     

基于SoC的嵌入式DRAM存储器内建自测试设计

内建自测试(Built-in Self Test,BIST)是测试片上系统(System on- Chip,SoC)中嵌入式存储器的重要技术;但是,利用BIST技术采用多种算法对嵌入式存储器进行测试仍面临诸多挑战;对此,提出了一种基于SoC的可以带有多种测试算法的嵌入式DRAM存储器BIST设计,所设计的测试电路可以复用状态机的状态,利用循环移位寄存器(Cyclic Shift Register,CSR)产生操作命令,利用地址产生电路产生所需地址;通过对3种BIST电路支持的算法,全速测试,面积开销3个方面的比较,表明提出的嵌入式DRAM存储器BIST设计在测试时间,测试故障覆盖率和测试面积开销等各方面都取得了较好的性能.